The present invention relates to phase detection circuits and methods of operation therefor, and more particularly, to phase lock detection circuits and methods of operation therefor.
Phase lock loop (PLL) and other phase control circuits typically require a determination of when the circuit has achieved phase synchronization, i.e., xe2x80x9cphase lock.xe2x80x9d It is generally desirable that this determination be made as accurately as possible in order to meet system performance requirements. In addition, a typical charge-pump type phase lock loop generates relatively large currents when in its acquisition mode, i.e., when it is seeking phase lock, and generates a relative smaller current when phase lock is achieved. Consequently, typical phase control systems attempt to quickly achieve phase lock and to maintain phase lock without oscillation in order to reduce power dissipation.
Towards this end, it is generally desirable in phase lock loops and other phase control circuits to accurately detect phase lock in a manner which is less susceptible to noise. It is also desirable to detect phase lock in a manner that is less prone to oscillation as the loop transitions in or out of phase lock.
In light of the foregoing, it is an object of the present invention to provide phase lock detection circuits and methods of operation therefor which can provide accurate and stable phase lock detection.
It is another object of the present invention to provide phase lock detection circuits and methods of operation therefor that have improved immunity to noise.
These and other objects, features and advantages are provided according to the present invention by phase lock detection circuits and methods of operation therefor in which a digital phase detection circuit produces a phase detect signal from first and second input signals provided thereto, and a stabilized phase lock detection circuit produces a phase lock indication signal responsive to the phase detect signal, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval.
The phase detection circuit preferably generates a window signal from the first input signal, the value of which is latched by a flip-flop circuit upon a transition of a delayed version of the second input signal to produce the phase detect signal. In this manner, a window detector is implemented that changes the phase detect signal to a logic state that indicates phase agreement when the second input signal has a phase delay with respect to the first input signal that falls within a time interval defined by the window signal.
The phase lock detection circuit may include a digital circuit that controls a digital count, the phase lock detection circuit changing the logic state of the phase lock detection signal when the digital count meets predetermined criteria. The predetermined criteria, e.g., a predetermined count threshold, may be programmably provided to the phase lock detection circuit. The phase lock detection circuit may alternatively include a circuit that controls a voltage across a capacitor, the phase lock detection circuit changing the logic state of the phase lock indication signal when the capacitor voltage meets predetermined criteria.
The present invention provides improved phase lock detection by utilizing circuitry that introduces hysteresis into the phase lock detection process. In this manner, oscillation or other instability caused by such factors as noise can be reduced and a more accurate indication of phase lock achieved.
In particular, according to the present invention, a phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval.
The phase detection circuit may include a first delay circuit configured to receive the first input signal and operative to produce a delayed first input signal therefrom, and a logic gate electrically coupled to the first delay circuit and operative to produce a window signal at an output thereof, the window signal representing a logic ANDing of the first input signal and the delayed first input signal. A second delay circuit is configured to receive the second input signal and operative to produce a delayed second input signal therefrom. A flip-flop circuit is electrically coupled to the logic gate and to the second delay circuit, receiving the window signal at a data input thereof and receiving the delayed second input signal at a clock input thereof and producing a phase detect signal therefrom that has a logic state corresponding to the logic state of the window signal at a transition of the delayed second input signal.
The stabilized phase lock indication circuit may include means for increasing a value when the phase detect signal is in its first logic state and for decreasing the value when the phase detect signal is in its second logic state. Means may be provided for changing the phase lock indication signal to its first logic state when the value meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the value meets a second predetermined criterion.
In a first embodiment according to the present invention, the stabilized phase lock indication circuit includes means for controlling a digital count responsive to the phase detect signal. Means are provided for changing the phase lock indication signal to its first logic state when the digital count meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the digital count meets a second predetermined criterion. The means for controlling a digital count may include means for increasing the digital count when the phase detect signal is in its first logic state and for decreasing the digital count when the phase detect signal is in its second logic state. The means for changing the phase lock indication signal may include means for changing the phase lock indication signal to its first logic state when the digital count increases above a predetermined threshold and means for changing the phase lock indication signal to its second logic state when the digital count decreases below the predetermined threshold.
In a second embodiment according to the present invention, the stabilized phase lock indication circuit includes a capacitor and means for controlling a capacitor voltage across the capacitor responsive to the phase detect signal. Means are provided for changing the phase lock indication signal to its first logic state when the capacitor voltage meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the capacitor voltage meets a second predetermined criterion.
The means for controlling a capacitor voltage may include means for charging the capacitor to increase the capacitor voltage when the phase detect signal is in its first logic state and for discharging the capacitor to decrease the capacitor voltage when the phase detect signal is in its second logic state. The means for changing the phase lock indication signal may include means for changing the phase lock indication signal to its first logic state when the capacitor voltage rises above a first predetermined threshold and for changing the phase lock indication signal to its second logic state when the capacitor voltage falls below a second predetermined threshold.
Related operating methods are also discussed.